Infinera is seeking a person experienced, with a track record in designing algorithms for soft decoding FEC that can approach channel capacity.
- The candidate will be part of a DSP algorithm design team. The application is a high throughput, 10% to 50% OH, and for use in fiber optic communication systems at greater than 100Gbit/sec data rates.
Must have working knowledge in the following areas:
- Binary BCH codes, Reed Solomon codes
- Turbo Product codes based on component binary BCH codes
- Binary LDPC codes, regular, irregular, spatially coupled
- Staircase codes, 400G ZR FEC
Education and Experience:
- 5+ years of experience as indicated in the following areas:
- Must have done previous designs in some of these, and understand ASIC implementation, parallelism, high throughput implementation, fixed point arithmetic, performance tradeoffs, and have understanding in critical timing closure issues in ASIC design.
- Must be strong in Matlab and C and C++ coding
- Must have great inter-personal working styles, and strong independent work ethic, and good communication skills